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SAMPLE

AND

HOLD

AIN−

AIN+

+1

−1

VP+

VP−

REFT

REFB

ADC

CORE

Sample and Hold

Analog-to-Digital Converter

Analog Input

THS1230

RS

VS+

VS−

RS

RSW

RSW

CI

CI

VCM

VCM

_

+

_

+

R

S t

1

2f

CLK

C

I

In(256)

–R

SW

THS1230

SLAS291B – OCTOBER 2000 – REVISED MARCH 2004

Figure 15. Analog Input Signal Flow

to give a differential output (VP+) – (VP–) = VP given by:

•

VP = (AIN+) – ( AIN–)

AIN greater than REFT or less than REFB causes ADC over-range, which is signaled by OVR going high when

the conversion result is output.

A first-order approximation for the equivalent analog input circuit of the THS1230 is shown in Figure 16. The

sample period of one half of a clock cycle. When a full-scale voltage step is applied, the input source provides

capacitor requires no input current and the equivalent input impedance is very high.

Figure 16. Simplified Equivalent Input Circuit

To maintain the frequency performance outlined in the specifications, the total source impedance should be

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