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FUNCTIONAL BLOCK DIAGRAM

12-Bit ADC

D[11:0]

Sample

and Hold

CLK

DGND

AGND

OVRNG

CON0

Timing Circuitry

REFT REFB

Internal

Reference

Circuit

CON1

3-State

Output

Buffers

EXTREF

Configuration

Control

Circuit

AIN+

AIN−

OE

THS1230

SLAS291B – OCTOBER 2000 – REVISED MARCH 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

ORDERING INFORMATION

PRODUCT

PACKAGE-

PACKAGE

SPECIFIED

PACKAGE

ORDERING

TRANSPORT MEDIA,

LEAD

TEMPERATURE

MARKING

NUMBER

QUANTITY

RANGE

THS1230

TSSOP-28

PW

0

°C to 70°C

TH1230

THS1230CPW

Tube, 50

THS1230

TSSOP-28

PW

0

°C to 70°C

TH1230

THS1230CPWR

Tape and reel, 2000

THS1230

TSSOP-28

PW

-40

°C to 85°C

TJ1230

THS1230IPW

Tube, 50

THS1230

TSSOP-28

PW

-40

°C to 85°C

TJ1230

THS1230IPWR

Tape and reel, 2000

THS1230

SOP-28

DW

0

°C to 70°C

TH1230

THS1230CDW

Tube, 20

THS1230

SOP-28

DW

0

°C to 70°C

TH1230

THS1230CDWR

Tape and reel, 1000

THS1230

SOP-28

DW

-40

°C to 85°C

TJ1230

THS1230IDW

Tube, 20

THS1230

SOP-28

DW

-40

°C to 85°C

TJ1230

THS1230IDWR

Tape and reel, 1000

(1)

For the most current specifictions and package information refer to our Web site at www.ti.com.

2