TMPR4955AF datasheet(45/168 Pages) TOSHIBA

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Chapter 2 Features

2-1

Chapter 2. Features

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TX49/H2 Processor Core

TX49/H2 Processor Core is a 64-bit RISC CPU core Toshiba developed based on the

architecture of MIPS for interactive consumer applications including Printer, Network

and set-top terminals.

•

IEEE754 compatible single and double precision FPU

The floating-point operations fully conform to the requirements of ANSI/IEEE Standard

754-1985, IEEE Standard for Binary Floating-Point Arithmetic.

As 32 general purpose register (32 FGRs), each of which is 64 bits wide and 2 control of

FPU registers (2 FCRs), each of which is 32bit wide. All floating-point instructions, as

defined in the MIPS ISA for the floating-point coprocessor, CP1, are processed by the

other hardware unit that executes integer instruction.

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Internal bus

Internal bus width

width

width iiiissss 64-bit, External bus width is 32-bit

64-bit, External bus width is 32-bit

Core and Cache are connect with 64-bit Internal bus. External bus is SysAD-bus I/F. This

interface is compatible with the TX4300, R4000, and R5000 system interfaces.

•

Power management

Internal: 1.5 V

I/O: 3.3 V

The TX49/H2 Processor support Power management mode (Halt, Doze)

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Maximum operating frequency

The TX49/H2 Processor’s maximum operating frequency is 200 MHz.

The SysAD-bus I/F and TX49/H2 Processor’s maximum operating frequency is set by

External pin (DivMode (1:0)).

Ex. Core’s operating frequency is 167 MHz/200 MHz

Div Mode (1:0)

Master Clock

CPU Clock

41.8 MHz/50 MHz

167 MHz/200 MHz

66.7 MHz/80 MHz

167 MHz/200 MHz

83.5 MHz/100 MHz

167 MHz/200 MHz

55.7 MHz/66.7 MHz

167 MHz/200 MHz

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Package

TX4955A: 160-pin QFP

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Part Number

TMPR4955AF-167

TMPR4955AF-200

TMPR4955AF Datenblatt(PDF) 45 Page - Toshiba Semiconductor

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