TMPR4955AF datasheet(85/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-13

returned data is sent if either the data requested by a read response were

returned or if the requested data could not be fetched. In this case, the processor

handles the result as a bus error exception.

Figure 6.2.12 illustrates a situation in which the slave state is autonomously

shifted to after a processor read request is issued.

Note:The timing of the SysADC bus and SysCmdP bus are the same as the timing

of the SysAD bus and SysCmd bus timing, respectively.

Figure 6.2.12 Processor Read Request Protocol

If the Release* signal is asserted, this means that either there is autonomous

shifting to the slave state or there is a response to the ExtRqst* signal assertion. In

this case, the processor can accept either a read response or an external request other

than a read response. If an external request other than a read response is issued, the

processor asserts Release* for 1 cycle, then autonomously shifts to the slave state

again after the external request process.

6.2.8.3

Processor write request protocols

Either of the two following protocols is used in issuing processor write requests.

•

The word write request protocol (see Note below) is used for double word,

partial double word, word or partial word writing.

Note: Words are called to differentiate from the block request protocol. It is

actually possible to transfer data in double word, partial double word, word,

or partial word units.

•

The block write request protocol is used for block write transactions.

The system interface is used in the master state to issue processor double word

write requests. Figure 6.2.13 illustrates processor non-coherent single word write

request cycles.

1. In order to issue a processor single word write request, a write command is sent to

345

Cycle

Master Clock

SysAD Bus

ValidOut*

Validln*

SysCmd Bus

Addr

Read

RdRdy*

WrRdy*

Release*

Master

Slave

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