AD9882ASLASHPCB datasheet(33/40 Pages) AD

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AD9882A

Rev. 0 | Page 33 of 40

change only when SCL is low. If SDA changes state while SCL is

high, the serial interface interprets that action as a start or stop

sequence.

The five components to serial bus operation are

•

Start signal

•

Slave address byte

•

Base register address byte

•

Data byte to read or write

•

Stop signal

When the serial interface is inactive (SCL and SDA are high),

communications are initiated by sending a start signal. The start

signal is a high-to-low transition on SDA while SCL is high.

This signal alerts all slaved devices that a data transfer sequence

is coming.

The first eight bits of data transferred after a start signal com-

prise a 7-bit slave address (the first seven bits) and a single R/W

bit (the eighth bit). The R/W bit indicates the direction of data

transfer: read from (1) or write to (0) the slave device. If the

transmitted slave address matches the address of the device

(set by the state of the SA input pin listed in Table 52), the

AD9882A acknowledges by bringing SDA low on the ninth

SCL pulse. If the addresses do not match, the AD9882A does

not acknowledge.

Table 52. Serial Port Addresses

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(MSB)

(LSB)

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the first bit of

the sequence. If the AD9882A does not acknowledge the master

device during a write sequence, the SDA remains high so the

master can gen-erate a stop signal. If the master device does not

acknowledge the AD9882A during a read sequence, the

AD9882A interprets this as end of data. The SDA remains

high so the master can generate a stop signal.

Writing data to specific control registers of the AD9882A

requires that the 8-bit address of the control register of interest

be written after the slave address has been established. This

control register address is the base address for subsequent write

operations. The base address autoincrements by one for each

byte of data written after the data byte intended for the base

address. If there are more bytes transferred than there are avail-

able addresses, the address does not increment and remains at

its maximum value of 0x1E. Any base address higher than 0x1E

does not produce an acknowledge signal.

Data is read from the control registers of the AD9882A in a

similar manner. Reading requires two data transfer operations:

•

The base address must be written with the R/W bit of the

slave address byte low to set up a sequential read operation.

•

Reading (the R/W bit of the slave address byte high) begins

at the previously established base address. The address of

the read register autoincrements after each byte is

transferred.

To terminate a read/write sequence to the AD9882A, a stop

signal must be sent. A stop signal comprises a low-to-high

transition of SDA while SCL is high. The timing for the

read/write is shown in Figure 18, and a typical byte transfer is

shown in Figure 19.

A repeated start signal occurs when the master device driving

the serial interface generates a start signal without first gener-

ating a stop signal to terminate the current communication.

This is used to change the mode of communication (read, write)

between the slave and master without releasing the serial

interface lines.

SDA

SCL

tDHO

tDSU

tSTASU

tSTAH

tBUFF

tDAL

tDAH

tSTOSU

Figure 18. Serial Port Read/Write Timing

BIT 7

SDA

SCL

ACK

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Figure 19. Serial Interface, Typical Byte Transfer

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