AD9882ASLASHPCB datasheet(35/40 Pages) AD

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AD9882A

Rev. 0 | Page 35 of 40

SYNC PROCESSING ENGINE

SYNC SLICER

This section describes the basic operation of the sync

processing engine (see Figure 20).

The purpose of the sync slicer is to extract the sync signal from

the green graphics channel. A sync signal is not present on all

graphics systems (only those with sync-on-green). The sync

signal is extracted from the green channel in a two-step process.

SOG input is clamped to its negative peak (typically 0.3 V

below the black level).

The signal goes to a comparator with a variable trigger

level, nominally 0.15 V above the clamped level. The

output signal is typically a composite sync signal

containing both Hsync and Vsync.

SYNC SEPARATOR

A sync separator extracts the Vsync signal from a composite

sync signal. It does this through a low-pass filter-like or

integrator-like operation. It works on the idea that the Vsync

signal stays active for a much longer time than the Hsync signal.

So, it rejects any signal shorter than a threshold value, which is

somewhere between an Hsync pulse width and a Vsync pulse

width.

The sync separator on the AD9882A is an 8-bit digital counter

with a 5 MHz clock. It works independently of the polarity of

the composite sync signal. Polarities are determined elsewhere

on the chip. The counter counts up when Hsync pulses are

present. But since Hsync pulses are relatively short in width, the

counter reaches only a value of N before the pulse ends. It then

starts counting down, eventually reaching 0 before the next

Hsync pulse arrives. The specific value of N varies for different

video modes, but is always less than 255. For example, with a

1 ms width Hsync, the counter only reaches 5 (1 µs/200 ns = 5).

When Vsync is present on the composite sync, the counter also

counts up. However, because the Vsync signal is much longer, it

counts to a higher number, M. For most video modes, M is at

least 255. So, Vsync can be detected on the composite sync

signal by detecting when the counter counts to higher than N.

The specific count that triggers detection (t) can be program-

med through the serial register (0x0E).

Once Vsync has been detected, a similar process detects when it

goes inactive. At detection, the counter first resets to 0, then

starts counting up when Vsync goes away. In a way similar to

the previous case, it detects the absence of Vsync when the

counter reaches the threshold count (T). In this way, it rejects

noise and/or serration pulses. Once Vsync is determined to be

absent, the counter resets to 0 and begins the cycle again.

SOG

HSYNC IN

HSYNC OUT

PIXEL CLOCK

HSYNC OUT

PLL

AD9882A

CLOCK

GENERATOR

VSYNC IN

ACTIVITY

DETECT

ACTIVITY

DETECT

SYNC STRIPPER

COMP

SYNC

NEGATIVE

PEAK

CLAMP

SYNC SEPARATOR

INTEGRATOR

VSYNC

1/S

ACTIVITY

DETECT

MUX 2

MUX 1

MUX 4

MUX 5

MUX 3

POLARITY

DETECT

POLARITY

DETECT

HSYNC

COAST

SOG OUT

VSYNC OUT

MUX 6

HSYNC

VSYNC

DVI

Figure 20. Sync Processing Block Diagram

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