AD9882ASLASHPCB datasheet(25/40 Pages) AD

25 / 40 page

AD9882A

Rev. 0 | Page 25 of 40

Hexadecimal

Address

Read and

Write or

Read Only

Bit

Default

Value

Function

0x16

Active Hsync

0 = Hsync from the Hsync input pin.

1 = Hsync from the SOG input.

Hsync Polarity

Detected

0 = Active low polarity detected.

1 = Active high polarity detected.

Active Vsync

0 = Vsync from the Vsync input pin.

1 = Vsync from SOG.

Vsync Polarity

Detected

0 = Active high polarity detected.

1 = Active low polarity detected.

Coast Polarity

Detected

0 = Active low polarity detected.

1 = Active high polarity detected.

This function works only with internal coast.

HDCP Keys

Detected

0 = Not detected.

1 = Detected.

0x17

R/W

7–0

0000 0000

Test Register

Must be set to 1000 0000 for proper operation.

0x18

R/W

7–0

0000 000X

Test Register

Must be set to 1100 000x for proper operation.

0x19

R/W

7–0

0000 010X

Test Register

Must be set to 0111 110x for proper operation.

0x1A

R/W

7–0

0011 1111

Test Register

Must be set to default for proper operation.

0x1B

R/W

1*** ****

MDA and MCL

0 = MDA and MCL three-stated.

1 = MDA and MCL not three-stated.

6–0

*111 0000

Test Register

Must be set to *110 0111 for proper operation.

0x1C

R/W

7–1

0000 111*

Test Register

Must be set to default for proper operation.

**** ***1

RXC Connect

0 = RX clock lines disconnected.

1 = RX clock lines connected.

0x1D

7–0

Test Register

Reserved for future use.

0x1E

7–0

Test Register

Reserved for future use.

1 The AD9882A updates the PLL divide ratio only when the LSBs are written to Register 0x02.

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