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MP4680 Datenblatt(PDF) 17 Page - NXP Semiconductors |
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MP4680 Datenblatt(HTML) 17 Page - NXP Semiconductors |
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17 / 28 page ![]() 1996 Oct 25 17 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4680 Notes to the characteristics 1. The values of the −(B − Y) and −(R − Y) colour difference input signals are for a 75% colour-bar signal. 2. The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600 Ω. 3. The white potentiometers affect the amplitudes of the RGB output signals including the white measurement pulses. 4. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources. 5. Sandcastle pulses are compared with internal threshold voltages independent of VP. The threshold voltages separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14 exceeds the defined internal threshold voltage. The internal threshold voltages (control bit SC5 = 0) are: 1.5 V for horizontal and vertical blanking pulses 3.5 V for horizontal pulses 6.0 V for the burst key pulse. The internal threshold voltages (control bit SC5 = 1) are: 1.5 V for horizontal and vertical blanking pulses 3.5 V for the burst key pulse. 6. A sandcastle pulse with a maximum voltage equal to (VP + 0.7 V) is obtained by limiting a 12 V sandcastle pulse. 7. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness. 8. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness. The maximum RGB outputs are determined via the I2C-bus under sub-address 0AH. When an RGB output exceeds the maximum voltage, peak drive limiting is delayed by one horizontal line. I2C-bus transceiver clock SCL (pin 28) fSCL input frequency range 0 − 100 kHz VIL LOW level input voltage −− 1.5 V VIH HIGH level input voltage 3.0 − 6.0 V IIL LOW level input current V28 = 0.4 V −10 −− µA IIH HIGH level input current −− 10 µA tL clock pulse LOW 4.7 −− µs tH clock pulse HIGH 4.0 −− µs tr rise time −− 1.0 µs tf fall time −− 0.3 µs I2C-bus transceiver data input/output SDA (pin 27) VIL LOW level input voltage −− 1.5 V VIH HIGH level input voltage 3.0 − 6.0 V IIL LOW level input current V27 = 0.4 V −10 −− µA IIH HIGH level input current −− 10 µA IOL LOW level output current V27 = 0.4 V 3.0 −− mA tr rise time −− 1.0 µs tf fall time −− 0.3 µs tSU;DAT data set-up time 0.25 −− µs SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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