SCF5249VM140 datasheet(27/56 Pages) FREESCALE

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Signal Descriptions

SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

Freescale Semiconductor

8.20.2 Test Reset/Development Serial Clock

The TEST[3:0] signals determine the function of the TRST/DSCLK dual-purpose pin. If

TEST[3:0]=0001, the DSCLK function is selected. If TEST[3:0]= 0000, the TRST function is selected.

TEST[3:0] should not be changed while RSTI = 1. When used as TRST, this pin will asynchronously reset

the internal JTAG controller to the test logic reset state, causing the JTAG instruction register to choose

the ìbypassî command. When this occurs, all the JTAG logic is benign and will not interfere with the

normal functionality of the SCF5249 processor. Although this signal is asynchronous, Freescale

recommends that TRST make only a 0 to 1 (asserted to negated) transition while TMS is held at a logic 1

value. TRST has an internal pullup so that if it is not driven low its value will default to a logic level of 1.

However, if TRST will not be used, it can either be tied to ground or, if TCK is clocked, it can be tied to

VDD. If it is tied to ground, it will place the JTAG controller in the test logic reset state immediately. If it

is tied to VDD, it will cause the JTAG controller (if TMS is a logic 1) to eventually end up in the test logic

reset state after 5 clocks of TCK. This pin is also used as the development serial clock (DSCLK) for the

serial interface to the Debug Module.The maximum frequency for the DSCLK signal is 1/5 the BCLKO

frequency.

8.20.3 Test Mode Select/Break Point

The TEST[3:0] signals determine the TMS/BKPT pin function. If TEST[3:0] =0001, the BKPT function

is selected. If TEST[3:0] = 0000, then the TMS function is selected. TEST[3:0] should not change while

RSTI = 1. When used as TMS, this input signal provides the JTAG controller with information to determine

which test operation mode should be performed. The value of TMS and current state of the internal

16-state JTAG controller state machine at the rising edge of TCK determine whether the JTAG controller

holds its current state or advances to the next state. This directly controls whether JTAG data or instruction

operations occur. TMS has an internal pullup so that if it is not driven low, its value will default to a logic

level of 1. However, if TMS will not be used, it should be tied to VDD. This pin also signals a hardware

breakpoint to the processor when in the debug mode.

8.20.4 Test Data Input/Development Serial Input

The TDI/DS is a dual-function pin. If TEST[3:0] = 0001, then DSI is selected. If TEST[3:0] = 0000, then

TDI is selected. When used as TDI, this input signal provides the serial data port for loading the various

JTAG shift registers composed of the boundary scan register, the bypass register, and the instruction

currently in the instruction register. This data shift occurs on the rising edge of TCK. TDI also has an

internal pullup so that if it is not driven low its value will default to a logic level of 1. However, if TDI will

not be used, it should be tied to VDD. This pin also provides the single-bit communication for the debug

module commands.

8.20.5 Test Data Output/Development Serial Output

The TDO/DSO is a dual-function pin. When TEST[3:0] = 0001, then DSO is selected. When TEST[3:0]

= 0000, TDO is selected. When used as TDO, this output signal provides the serial data port for outputting

SCF5249VM140 Datenblatt(PDF) 27 Page - Freescale Semiconductor, Inc