SCF5249VM140 datasheet(17/56 Pages) FREESCALE

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Signal Descriptions

SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

Freescale Semiconductor

8.2

GPIO

Many pins have a GPIO as first or second function. If GPIO is second function, following rules apply:

•

General purpose input is always active, regardless of state of pin.

•

General purpose output or primary output is determined by value written to GPIO function select

•

Power-on reset function is not GPIO.

8.3

SCF5249 Bus Signals

These signals provide the external bus interface to the SCF5249.

8.3.1

Address Bus

•

The address bus provides the address of the byte or most significant byte of the word or longword

being transferred.The address lines also serve as the DRAM address pins, providing multiplexed

row and column address signals.

•

Bits 23 down to 1 and 25 of the address are available. A25 is intended to be used with 256 Mbit

DRAM’s. Signals are named:

•

A[23:1]

•

A[25]/GPO8

8.3.2

Read-Write Control

This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and

a high is a read cycle.

8.3.3

Output Enable

The OE signal is intended to be connected to the output enable of asynchronous memories connected to

chip selects. During bus read cycles, the ColdFire processor will drive OE low.

8.3.4

Data Bus

The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5249 on the

rising clock edge. The port width for each chip-select and DRAM bank are programmable. The data bus

uses a default configuration if none of the chip-selects or DRAM bank match the address decode. All 16

bits of the data bus are driven during writes, regardless of port width or operand size.

8.3.5

Transfer Acknowledge

The TA/GPIO20 pin is the transfer acknowledge signal.

SCF5249VM140 Datenblatt(PDF) 17 Page - Freescale Semiconductor, Inc

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