ADL5567ACPZN-R7 datasheet(17/23 Pages) AD

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Data Sheet

ADL5567

Rev. A | Page 17 of 23

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

200

400

600

800

1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

3.3V LP, SE

3.3V LP, DIFF

5V HP, SE

5V HP, DIFF

Figure 44. HD2 for Single-Ended (SE) and Differential (DIFF) Configurations

vs. Frequency, VOUT = 2 V p-p, RL = 200 Ω

INPUT AND OUTPUT EQUIVALENT CIRCUITS

The differential input and outptut impedance can be modeled

by simple RLC equivalent circuits as shown in Figure 45. Figure 34

shows the comparison of the measured and modeled impedances

for the input network. Likewise, Figure 35 shows the same

comparison for the output network.

VIP

VIN

100Ω

50Ω

12nF

0.4nF

0.3pF

VOP

VON

10Ω

22Ω

1.4nF

1.5nF

1.4nF

0.8pF

Figure 45. Model of Differential Input and Output Circuit

GAIN ADJUSTMENT AND INTERFACING

The effective gain of the ADL5567 can be reduced by adding two

resistors in series with the inputs to reduce the gain.

ADL5567

0.1µF

50Ω

500Ω

5Ω

0.1µF

RSERIES

RSHUNT

RSERIES

–

Figure 46. Gain Adjustment Using a Series Resistor

To find RSERIES for a given AV gain and RL, use the following

equation:

500

SERIES



×−





(6)

The necessary shunt component, RSHUNT, to match to the source

impedance, RS, can be expressed as

100

−

SERIES

SHUNT

(7)

The shunt resistor values for multiple target voltage gains are listed

in Table 5. The source resistance and input impedance need

careful attention when using Equation 5. The input impedance

of the ADL5567 and the reactance of the ac coupling capacitors

must be considered before assuming that they make a negligible

contribution.

To calculate the gain (AV) for a given RSERIES and RL, use the

following equation:

























SERIES

500

(8)

Note that Equation 8 only gives the absolute gain and does not

take into account that the circuit introduces a 180° phase shift.

To account for this phase shift, multiply the product of

Equation 8 by −1.

Table 5. Differential Gain Adjustment Using Series Resistor

Target Voltage Gain (dB)

RS (Ω)

RSERIES (Ω)

RSHUNT (Ω)

426.1

52.7

374.4

53.1

328.2

53.5

287.1

250.4

54.5

217.7

55.1

188.6

55.8

162.7

56.6

139.5

57.5

118.9

58.6

100.5

59.9

84.2

61.4

69.6

63.2

56.6

65.3

67.8

34.6

70.9

25.4

74.7

17.2

79.5

9.9

85.7

3.4

93.7

EFFECT OF LOAD CAPACITANCE

Load capacitance, including stray capacitance from PCB traces,

affect the bandwidth and flatness of the ADL5567 frequency

response, resulting in excessive peaking. Adding external series

resistors to each output isolates the load capacitance from the

outputs, and reduces the peaking effectively. Respective frequency

responses resulting from the addition of 1.5 pF and 3 pF differential

load capacitance (CLD) as well as series resistance (RSE) of 15 Ω

are shown in Figure 47.

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