ADL5567ACPZN-R7 datasheet(20/23 Pages) AD

20 / 23 page

ADL5567

Data Sheet

Rev. A | Page 20 of 23

SOLDERING INFORMATION AND RECOMMENDED

LAND PATTERN

Figure 53 shows the recommended land pattern for the ADL5567.

The ADL5567 is contained in a 4 mm × 4 mm LFCSP package,

which has an exposed ground pad (EP). This pad is internally

connected to the ground of the chip. To minimize thermal

impedance and ensure electrical performance, solder the pad to

the low impedance ground plane on the PCB. To further reduce

thermal impedance, it is recommended that the ground planes

on all layers under the paddle be stitched together with vias.

For more information on land pattern design and layout, refer

to the AN-772 Application Note, A Design and Manufacturing

Guide for the Lead Frame Chip Scale Package (LFCSP).

The land pattern on the ADL5567 evaluation board provides a

simulated thermal resistance (θJA) of 56 °C/W.

13 MILS

39 MILS

12 MILS

91 MILS

13.7 MILS

19.7 MILS

Figure 53. Recommended Land Pattern

EVALUATION BOARD

Figure 54 shows the schematic of the ADL5567 evaluation board.

The evaluation board is powered by a single supply in the 3 V to

5 V range. The power supply is decoupled by 10 µF and 0.1 µF

capacitors. Inductors L1 and L2 decouple the ADL5567 from the

power supply. Table 7 details the various configuration options of

the evaluation board.

Figure 55 and Figure 56 show the component and circuit side

layouts of the evaluation board.

The balanced input and output interfaces are converted to single-

ended with a pair of baluns (Mini-Circuits TCM1-43X+). The

baluns at the input, T1 and T2, provide a 50 Ω single-ended to

differential transformation. The output baluns, T3 and T4, and the

matching components are configured to provide a 200 Ω to 50 Ω

impedance transformation with an insertion loss of about 11 dB.

ADL5567ACPZN-R7 Datenblatt(PDF) 20 Page - Analog Devices