PIC18F44J10-ESLASHML datasheet(29/358 Pages) MICROCHIP

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Preliminary

DS39682C-page 27

PIC18F45J10 FAMILY

2.6.1

OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several

aspects of the device clock’s operation, both in full

power operation and in power-managed modes.

The System Clock Select bits, SCS1:SCS0, select the

clock source. The available clock sources are the

primary clock (defined by the FOSC2:FOSC0 configu-

ration bits), the secondary clock (Timer1 oscillator) and

the internal oscillator. The clock source changes after

one or more of the bits are written to, following a brief

clock transition interval.

The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)

bits indicate which clock source is currently providing

the device clock. The OSTS bit indicates that the

Oscillator Start-up Timer (OST) has timed out and the

primary clock is providing the device clock in primary

clock modes. The T1RUN bit indicates when the

Timer1 oscillator is providing the device clock in sec-

ondary clock modes. In power-managed modes, only

one of these bits will be set at any time. If neither of

these bits are set, the INTRC is providing the clock, or

the internal oscillator has just started and is not yet

stable.

The IDLEN bit determines if the device goes into Sleep

mode or one of the Idle modes when the SLEEP

instruction is executed.

The use of the flag and control bits in the OSCCON

“Power-Managed Modes”.

2.6.1.1

System Clock Selection and the

FOSC2 Configuration Bit

The SCS bits are cleared on all forms of Reset. In the

device’s default configuration, this means the primary

oscillator defined by FOSC1:FOSC0 (that is, one of the

HC or EC modes) is used as the primary clock source

on device Resets.

The default clock configuration on Reset can be changed

with the FOSC2 configuration bit. The effect of this bit is

to set the clock source selected when SCS1:SCS0 = 00.

When FOSC2 = 1 (default), the oscillator source

defined by FOSC1:FOSC0 is selected whenever

SCS1:SCS0 = 00. When FOSC2 = 0, the INTRC oscilla-

tor is selected whenever SCS1:SCS2 = 00. Because the

SCS bits are cleared on Reset, the FOSC2 setting also

changes the default oscillator mode on Reset.

Regardless of the setting of FOSC2, INTRC will always

be enabled on device power-up. It will serve as the

clock source until the device has loaded its configura-

tion values from memory. It is at this point that the

FOSC configuration bits are read and the oscillator

selection of operational mode is made.

Note that either the primary clock or the internal

oscillator will have two bit setting options, at any given

time, depending on the setting of FOSC2.

2.6.2

OSCILLATOR TRANSITIONS

PIC18F45J10 family devices contain circuitry to

prevent clock “glitches” when switching between clock

sources. A short pause in the device clock occurs dur-

ing the clock switch. The length of this pause is the sum

of two cycles of the old clock source and three to four

cycles of the new clock source. This formula assumes

that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power-Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 Control regis-

ter (T1CON<3>). If the Timer1 oscillator is

not enabled, then any attempt to select a

secondary clock source when executing a

SLEEP

instruction will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before

executing the SLEEP instruction or a very

long delay may occur while the Timer1

oscillator starts.

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