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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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PIC18F44J10-E/ML Datenblatt(PDF) 97 Page - Microchip Technology |
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PIC18F44J10-E/ML Datenblatt(HTML) 97 Page - Microchip Technology |
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97 / 358 page  © 2007 Microchip Technology Inc. Preliminary DS39682C-page 95 PIC18F45J10 FAMILY TABLE 9-3: PORTA I/O SUMMARY Pin Function TRIS Setting I/O I/O Type Description RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D input channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D input channel 1 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RA2/AN2/ VREF-/CVREF RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA A/D input channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D and comparator voltage reference low input. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RA3/AN3/VREF+RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D input channel 3 and Comparator C1+ input. Default input configuration on POR. VREF+ 1 I ANA A/D and comparator voltage reference high input. RA5/AN4/SS1/ C2OUT RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D input channel 4. Default configuration on POR. SS1 1 I TTL Slave select input for MSSP1 (MSSP1 module). C2OUT 0 O DIG Comparator 2 output; takes priority over port data. OSC2/CLKO OSC2 x O ANA Main oscillator feedback output connection (HS mode). CLKO x O DIG System cycle clock output (FOSC/4) in RC and EC Oscillator modes. OSC1/CLKI OSC1 x I ANA Main oscillator input connection. CLKI x I ANA Main clock input connection. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). |
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