PIC18F44J10-ESLASHML datasheet(71/358 Pages) MICROCHIP

71 / 358 page

Preliminary

DS39682C-page 69

PIC18F45J10 FAMILY

EECON1: DATA EEPROM CONTROL REGISTER 1

U-0

R/W-0

R/W-x

R/W-0

R/S-0

U-0

—

FREE

WRERR

WREN

—

bit 7

bit 0

bit 7-5

Unimplemented: Read as ‘0’

bit 4

FREE: Flash Row Erase Enable bit

= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

= Perform write only

bit 3

WRERR: Flash Program/Data EEPROM Error Flag bit

= A write operation is prematurely terminated (any Reset during self-timed programming in

normal operation, or an improper write attempt)

= The write operation completed

bit 2

WREN: Flash Program/Data EEPROM Write Enable bit

= Allows write cycles to Flash program/data EEPROM

= Inhibits write cycles to Flash program/data EEPROM

bit 1

WR: Write Control bit

= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.)

= Write cycle to the EEPROM is complete

bit 0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

S = Bit can be set by software, but not cleared

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

PIC18F44J10-E/ML Datenblatt(PDF) 71 Page - Microchip Technology

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