Internet Data Sheet

Rev.1.22, 2007-08

7

03292006-D7GM-ZBSS

HY[B/E]18L512320BF-7.5

512-Mbit Mobile-RAM

1.4

Pin Definition and Description

TABLE 4

Pin Description

Ball

Type

Detailed Function

CLK

Input

Clock: all inputs are sampled on the positive edge of CLK.

CKE

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, device input

buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF

REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or

SUSPEND (access in progress). CKE is synchronous for POWER-DOWN entry and exit and for

SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers, excluding

CLK and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during

SELF REFRESH.

CS

Input

Chip Select: All commands are masked when CS is registered high. CS provides for external bank

selection on systems with multiple memory banks. CS is considered part of the command code.

RAS, CAS,

WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DQ0 - DQ31

I/O

Data Inputs/Output: Bi-directional data bus (32 bit)

DQM0 -

DQM3

Input

Input/Output Mask: input mask signal for WRITE cycles and output enable for READ cycles. For

WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as an output enable and

places the output buffers in High-Z state when HIGH (two clocks latency).

DQM0 corresponds to the data on DQ0 - DQ7; DQM1 to the data on DQ8 - DQ15; DQM2 to the

data on DQ16 - DQ23; DQM3 to the data on DQ24 - DQ31.

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or

PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be

loaded during a MODE REGISTER SET command (MRS or EMRS).

A0 - A12

Input

Address Inputs: defines the row address during an ACTIVE command cycle. A0 - A8 define the

column address during a READ or WRITE command cycle. In addition, A10 (= AP) controls Auto

Precharge operation at the end of the burst read or write cycle. During a PRECHARGE command,

A10 (= AP) in conjunction with BA0, BA1 controls which bank(s) are to be precharged: if A10 is

HIGH, all four banks will be precharged regardless of the state of BA0 and BA1; if A10 is LOW, BA0,

BA1 define the bank to be precharged. During MODE REGISTER SET commands, the address

inputs hold the op-code to be loaded.

V

DDQ

Supply

I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity:

V

V to 1.95 V

V

SSQ

Supply

I/O Ground

V

DD

Supply

Power Supply: Power for the core logic and input buffers,

V

V

SS

Supply

Ground

N.C.

–

No Connect