Internet Data Sheet

Rev.1.22, 2007-08

3

03292006-D7GM-ZBSS

HY[B/E]18L512320BF-7.5

512-Mbit Mobile-RAM

1Overview

1.1

Features

• 4 banks

× 4 Mbit × 32 organization (dual-die)

• Fully synchronous to positive clock edge

• Four internal banks for concurrent operation

• Programmable CAS latency: 2, 3

• Programmable burst length: 1, 2, 4, 8 or full page

• Programmable wrap sequence: sequential or interleaved

• Programmable drive strength: full, 1/2, 1/4 and 1/8

• Auto refresh and self refresh modes

• Refresh cycles:

– 8192 refresh cycles / 64 ms

• Auto precharge

• Commercial (-0

°C to +70°C) and Extended (-25°C to +85°C) operating temperature range

• Package:

– Dual-Die 90-ball PG-TFBGA package (13.0

× 8.0 × 1.2 mm)

Power Saving Features

• Low supply voltages:

V

• Optimized self refresh (

I

• Programmable Partial Array Self Refresh (PASR)

• Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor

• Power-Down and Deep Power Down modes

TABLE 1

Performance

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Part Number Speed Code

- 7.5

Unit

Speed Grade

133

MHz

Access Time (

t

CL = 2 or 3

6.5

ns

Clock Cycle Time (

t

CL = 3

7.5

ns

CL = 2

9.5

ns