BMP581 datasheet(29/75 Pages) BOSCH

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Bosch Sensortec | BST-BMP581-DS004-11

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Document number: BST-BMP581-DS004-11

as well as in the event of applications for industrial property rights

FIFO threshold interrupt during FIFO read. Interrupt generation is not blocked during an ongoing FIFO read. If the

fill level drops below the threshold during a FIFO read, and reaches the threshold again (due to a new sample being

wrtten to the FIFO), the interrupt will be asserted. If such behavior is not wanted, it can be avoided by any of the

following strategies:



Use non-latched interrupts, and ignore the interrupt during read.



Read-out the FIFO fast enough that the fill level is 2 frames below the watermark level before the next sample is

taken (which occurs ~1/ODR seconds after the interrupt assertion).

4.8NVM Programmability

The BMP581 contains a non volatile memory (NVM) that contains trimming and configuration parameters that are

used internaly by the sensor. In addition, there is a user range.

User write to the memory is restricted to the NVM User Range. User read can also be performed to the other NVM

addresses.

4.8.1 NVM User Range

The host can write and read the memory of the user range. The range is located at addresses 0x20-0x22. Each

address holds 2 bytes. This memory area may be used for an end-of-line trim at OEM or ODM sites. The maximum

number of writes during the lifetime of BMP581 is specified by NNVM_WRITE. During the write procedure, the power

supply to the BMP581 must be stable, and no soft-reset must be issued. Otherwise, permanent damage to the device

may occur.

In order to read or write the entire user range, the read/write procedure has to be executed repeatedly for the three

addresses 0x20-0x22. Reads always follow the procedure given in chapter 3.8.1.2.

4.8.1.1

NVM Read procedure



Switch to STANDBY mode by writing ODR_CONFIG.pwr_mode and ensuring that DEEP STANDBY is disabled6



Wait until STATUS.nvm_rdy is equal to 1



Write the NVM_ADDR register, with nvm_row_address containing the address to read, and nvm_prog_en set to 0

Write the USR_READ sequence (0x5D, 0xA5) into to CMD register. All write transactions to NVM_ADDR and

USR_READ must be individual transactions, and must not be combined in burst writes.



Wait until STATUS.nvm_rdy is equal to 1. This takes approximately 200 μs



Read the data from the NVM_DATA_MSB and NVM_DATA_LSB registers



Check for errors in STATUS.nvm_err, STATUS.nvm_cmd_err. Read data will not be valid if one of the error flags is

set

4.8.1.2

NVM Write procedure



Switch to STANDBY mode by writing ODR_CONFIG.pwr_mode and ensuring that DEEP STANDBY is disabled7



Wait until STATUS.nvm_rdy is equal to 1



Write the NVM register, with nvm_row_address containing the address to write, and nvm_prog_en set to 1



Write the data to be programmed to NVM_DATA_MSB and NVM_DATA_LSB

Write the USR_PROG sequence (0x5D, 0xA0) into the CMD register. All write transactions to NVM_ADDR, NVM_-

DATA_MSB and NVM_DATA_LSB and USR_READ must be individual transactions, and must not be combined in

burst writes.



Wait untill STATUS.nvm_rdy is equal to 1.This takes approximately 10 ms



Check for errors in STATUS.nvm_err, STATUS.nvm_cmd_err. The write was not successfully performed if one of the

error flags is set



Reset NVM_ADDR.nvm_prog_en to 0

DEEP STANDBY is disabled when at least one of the conditions described in Chapter 4.3.2 is not fulfilled

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