ADE9178 datasheet(84/122 Pages) AD

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Data Sheet

ADE9178

analog.com

Rev. A | 84 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

000

Evaluation Over 64 Samples.

001

Evaluation Over 128 Samples.

010

Evaluation Over 256 Samples.

011

Evaluation Over 512 Samples.

100

Evaluation Over 1024

Samples.

101

Evaluation Over 2048

Samples.

110

Evaluation Over 4096

Samples.

111

Disable No Load Threshold.

RD_RST_EN

Energy Register Reset on

Read Enable. Set this bit to

enable the energy register

read with reset feature. If this

bit is set, when one of the

energy accumulation registers

is read, it is reset and begins

accumulating energy from zero.

0x0

R/W

EGY_LD_ACCUM

Energy Register Update Mode.

If this bit is equal to zero,

the internal energy register is

added to the user-accessible

energy register. If the bit is

set, the internal energy register

overwrites the user-accessible

energy register when the

EGYRDY event occurs.

0x0

R/W

EGY_TMR_MODE

Energy Accumulation Mode.

This bit determines whether

energy is accumulated based

on time (in ms) or zero-

crossing events configured in

the EGY_TIME register.

0x0

R/W

Time Based Accumulation.

Accumulate energy for fixed

time duration (in ms).

Zero-Crossing Based

Accumulation. Accumulate

energy based on the

zero crossing selected by

the ZX_SEL bits in the

ZX_LP_SEL register. Note, it

is not recommended to use

line-cycle accumulation mode.

For more details, see Silicon

Anomaly section.

EGY_PWR_EN

Energy Accumulators Enable.

Set this bit to enable the

energy accumulator, when the

run bit is also set.

0x0

R/W

0x0D6

WFS_CONFIG

[31:19]

RESERVED

Reserved.

0x0

AUX5_WFS_EN

Set to Enable Auxiliary 5

Channel Waveform Streaming.

0x0

R/W

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