ADE9178 datasheet(93/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 93 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

timeout on phase B. This

means that a zero crossing on

the phase B voltage is missing.

ZXTOAV

Phase A Voltage Zero-Crossing

Timeout. This bit is set

to indicate a zero-crossing

timeout on phase A. This

means that a zero crossing on

the Phase A voltage is missing.

0x0

R/W1C

SEQERR

Phase Sequence Error

Occurred on Voltage Zero

Crossings. This bit is set if

zero crossings on three voltage

phases does not follow phase

A − phase B − phase C

sequence.

0x0

R/W1C

RSTDONE

Reset Completed and Ready

for SPI Communication. This

bit is set to indicate that reset

is complete and board is ready

for SPI communication.

0x0

R/W1C

CRC_CHG

CRC Changed. This bit is

set if any of the registers

monitored by the configuration

The CRC_RSLT register holds

the new configuration register

CRC value.

0x0

R/W1C

VANLOAD

Total Apparent Energy No Load

Condition Changed. This bit is

set when one or more phase of

total apparent energy enters or

exits the no load condition.

0x0

R/W1C

WATTNLOAD

Total Active Energy No Load

Condition Changed. This bit is

set when one or more phase

of total active energy enters or

exits the no load condition.

0x0

R/W1C

ISUMMISMTCH

ISUM RMS Mismatch. This bit

is set to indicate a change

in the relationship between

ISUMRMS and ISUMLVL.

0x0

R/W1C

PF_RDY

Power Factor Data Ready.

This bit is set to indicate that

power factor measurements

are updated, every 1 sec.

0x0

R/W1C

RMSONERDY

One-Cycle RMS Data Ready.

This bit is set when the one-

cycle RMS values are updated.

0x0

R/W1C

CF2

CF2 Pulse Issued. This bit

is set when a CF2 pulse is

issued, when the CF2 pin goes

from a high to low state.

0x0

R/W1C

CF1

CF1 Pulse Issued. This bit

is set when a CF1 pulse is

0x0

R/W1C

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