ADE9178 datasheet(99/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 99 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

swell condition, as calculated

by RMSONE.

AUX3SWELLONE

Auxiliary 3 Channel Swell

Condition Detected. This bit is

set when the AUX3 channel

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

AUX2SWELLONE

Auxiliary 2 Channel Swell

Condition Detected. This bit is

set when the AUX2 channel

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

AUX1SWELLONE

Auxiliary 1 Channel Swell

Condition Detected. This bit is

set when the AUX1 channel

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

AUX0SWELLONE

Auxiliary 0 Channel Swell

Condition Detected. This bit is

set when the AUX0 channel

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

CISWELLONE

Phase C Current Swell

Condition Detected. This bit is

set when the phase C current

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

CVSWELLONE

Phase C Voltage Swell

Condition Detected. This bit is

set when the phase C voltage

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

BISWELLONE

Phase B Current Swell

Condition Detected. This bit is

set when the phase B current

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

BVSWELLONE

Phase B Voltage Swell

Condition Detected. This bit is

set when the phase B voltage

is in the swell condition and

is zero when it is not in a

0x0

R/W1C

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