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SX28AC/SS Datenblatt(PDF) 14 Page - Parallax Inc

Teilenummer SX28AC/SS
Bauteilbeschribung  Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug
PDF  51 Pages
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Hersteller  PARALLAX [Parallax Inc]
Direct Link  https://www.parallax.com/
Logo PARALLAX - Parallax Inc

SX28AC/SS Datenblatt(HTML) 14 Page - Parallax Inc

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Parallax SX20AC/SX28AC
www.parallax.com
© Parallax Inc.
Page 14 of 51
Rev 1.6 11/20/2006
4.3.
OPTION Register
When the OPTIONX bit in the FUSE word is cleared, bits
7 and 6 of the OPTION register function as described
below.
When the OPTIONX bit is set, bits 7 and 6 of the
OPTION register read as ‘1’s.
RTW
RTCC/W register selection:
0 = Register 01h addresses W
1 = Register 01h addresses RTCC
RTE_IE RTCC edge interrupt enable:
0 = RTCC roll-over interrupt is enabled
1 = RTCC roll-over interrupt is disabled
RTS
RTCC increment select:
0= RTCC increments on internal instruction
cycle
1 = RTCC increments upon transition on RTCC
pin
RTE_ES RTCC edge select:
0 = RTCC increments on low-to-high transitions
1 = RTCC increments on high-to-low transitions
PSA
Prescaler Assignment:
0 = Prescaler is assigned to RTCC, with divide
rate determined by PS0-PS2 bits
1 = Prescaler is assigned to WDT, and divide
rate on RTCC is 1:1
PS2-PS0: Prescaler divider (see table below)
Table 4-2: Prescaler Divider Ratios
PS2, PS1, PS0
RTCC Divide
Rate
Watchdog Timer
Divide Rate
000
1:2
1:1
001
1:4
1:2
010
1:8
1:4
011
1:16
1:8
100
1:32
1:16
101
1:64
1:32
110
1:128
1:64
07h111
1:256
1:128
Upon reset, all bits in the OPTION register are set to 1.
RTW
RTW_IE
RTS
RTE_ES
PSA
PS2
PS1
PS0
Bit 7
Bit 0



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