68HC05PL4B datasheet(71/98 Pages) FREESCALE

71 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

INSTRUCTION SET

REV 2.0

12-3

12.1.7 Indexed, 16-Bit Offset

Indexed, 16-bit offset instructions are three-byte instructions that can access data

with variable addresses at any location in memory. The CPU adds the unsigned

byte in the index register to the two unsigned bytes following the opcode. The sum

is the conditional address of the operand. The rst byte after the opcode is the

high byte of the 16-bit offset; the second byte is the low byte of the offset. These

instructions can address any location in memory.

Indexed, 16-bit offset instructions are useful for selecting the kth element in an

n-element table anywhere in memory.

As with direct and extended addressing, the Freescale assembler determines the

shortest form of indexed addressing.

12.1.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true,

the CPU nds the conditional branch destination by adding the signed byte

following the opcode to the contents of the program counter. If the branch

condition is not true, the CPU goes to the next instruction. The offset is a signed,

two’s complement byte that gives a branching range of –128 to +127 bytes from

the address of the next location after the branch instruction.

When using the Freescale assembler, the programmer does not need to calculate

the offset, because the assembler determines the proper offset and veri es that it

is within the span of the branch.

12.1.9 Instruction Types

The MCU instructions fall into the following v e categories:

•

Read-Modify-Write Instructions

•

Jump/Branch Instructions

•

Bit Manipulation Instructions

•

Control Instructions

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC05PL4B Datenblatt(PDF) 71 Page - Freescale Semiconductor, Inc