Data Sheet

ADRF5051

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 8 of 18

Figure 3. Pin Configuration (Top View)

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

EN

Enable Input. See Table 7 for the truth table and Figure 6 for the interface schematic.

2

V1

Control Input 1. See Table 7 for the truth table and Figure 5 for the interface schematic.

3, 5, 9, 11 to 13, 15 to 17,

19 to 21, 23

GND

Grounds. The GND pins must be connected to the RF and DC ground of the PCB.

4

RFC

RF Common Port. No DC blocking capacitor is required when the RF line potential is equal to 0V DC. See Figure 4 for the

interface schematic.

6

VSS

Negative Supply Voltage. See Figure 9 for the interface schematic.

7

LS

Logic Select Input. See Table 7 for the truth table and Figure 7 for the interface schematic.

8

VDD

Positive Supply Voltage. See Figure 8 for the interface schematic.

10

RF4

RF Throw Port 4. No DC blocking capacitor is required when the RF line potential is equal to 0V DC. See Figure 4 for the

interface schematic.

14

RF3

RF Throw Port 3. No DC blocking capacitor is required when the RF line potential is equal to 0V DC. See Figure 4 for the

interface schematic.

18

RF2

RF Throw Port 2. No DC blocking capacitor is required when the RF line potential is equal to 0V DC. See Figure 4 for the

interface schematic.

22

RF1

RF Throw Port 1. No DC blocking capacitor is required when the RF line potential is equal to 0V DC. See Figure 4 for the

interface schematic.

24

V2

Control Input 2. See Table 7 for the truth table and Figure 5 for the interface schematic.

EPAD

Exposed Pad. Exposed pad must be connected to the RF and DC ground.