Data Sheet

ADRF5051

THEORY OF OPERATION

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Rev. A | 15 of 18

RF INPUT AND OUTPUT

All of the RF ports (RFC and RF1 to RF4) are biased to ground

potential, and a DC blocking capacitor is not required at the RF

ports if the RF line potential is equal to ground. The RF ports are

internally matched to 50Ω. Therefore, external matching networks

are not required.

The insertion loss path conducts the RF signal between the select-

ed RF throw port and the RF common port. All unselected RF throw

ports have high isolation from RFC and the remaining RF throw

ports.

POWER SUPPLY

The ADRF5051 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

The ideal power-up sequence is as follows:

1. Connect GND to ground.

2. Power up VDD and VSS. Powering up VSS after VDD avoids

current transients on VDD during ramp up.

3. Apply a control voltage to the digital control inputs (EN, LS, V1,

and V2). Applying a control voltage to the digital control inputs

before the VDD supply can inadvertently forward bias and

damage the internal ESD protection structures. Use a series

1kΩ resistor to limit the current flowing into the control pin in

such cases. If the control pins are not driven to a valid logic

state (that is, the controller output is in a high impedance state)

after VDD is powered up, it is recommended to use a pull-up or

pull-down resistor.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

SINGLE-SUPPLY OPERATION

The ADRF5051 can operate with a single positive supply voltage

applied to the VDD pin and the VSS pin connected to ground. In

single-supply operation, the switching characteristics, linearity, and

power handling performance are derated, see Table 2 for additional

information.