Data Sheet

ADRF5051

THEORY OF OPERATION

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Rev. A | 14 of 18

The ADRF5051 integrates a CMOS-/LVTTL-compatible control in-

terface. The digital control input pins (EN, LS, V1, and V2) control

the state of the RF paths (see Table 7).

The logic levels applied to the V1 and V2 pins determine which RF

throw (RFx) port is in the insertion loss state (selected or on). The

remaining three RFx ports are in the isolation state (unselected or

off).

The LS pin allows the user to invert the RFx port selection logic

(see the truth table for V1 and V2, Table 7). See the application

example of this feature in the Back-to-Back Application section.

When the EN pin is logic high, all four RF paths are in an isolation

state regardless of the logic state of the LS, V1, and V2 pins.

The RFx ports are terminated to internal 50Ω resistors, and RFC

becomes reflective.

Table 7. Control Voltage Truth Table

Digital Control Inputs

RFx Paths

EN

LS

V1

V2

RFC to RF1

RFC to RF2

RFC to RF3

RFC to RF4

Low

Low

Low

Low

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

Low

Low

High

Low

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

Low

Low

High

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

Low

Low

High

High

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

Low

High

Low

Low

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

Low

High

High

Low

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

Low

High

Low

High

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

High

High

High

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

High

Low or high

Low or high

Low or high

Isolation (off)

Isolation (off)

Isolation (off)

Isolation (off)