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M40SZ100Y Datenblatt(PDF) 12 Page - STMicroelectronics

Teilenummer M40SZ100Y
Bauteilbeschribung  5V or 3V NVRAM supervisor for LPSRAM
PDF  25 Pages
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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M40SZ100Y Datenblatt(HTML) 12 Page - STMicroelectronics

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Operation
M40SZ100Y, M40SZ100W
12/25
2.2
Power-on reset output
All microprocessors have a reset input which forces them to a known state when starting.
The M40SZ100Y/W has a reset output (RST) pin which is guaranteed to be low by VPFD
(see Table 7 on page 17). This signal is an open drain configuration. An appropriate pull-up
resistor to VCC should be chosen to control the rise time. This signal will be valid for all
voltage conditions, even when VCC equals VSS (with valid battery voltage).
Once VCC exceeds the power failure detect voltage VPFD, an internal timer keeps RST low
for tREC to allow the power supply to stabilize.
2.3
Reset input (RSTIN)
The M40SZ100Y/W provides one independent input which can generate an output reset.
The duration and function of this reset is identical to a reset generated by a power cycle.
Table 3 and Figure 8 illustrate the AC reset characteristics of this function. Pulses shorter
than tRLRH will not generate a reset condition. RSTIN is internally pulled up to VCC through a
100k
Ω resistor.
Figure 8.
RSTIN timing waveform
1.
With pull-up resistor
Table 3.
Reset AC characteristics
2.4
Battery low pin
The M40SZ100Y/W automatically performs battery voltage monitoring upon power-up, and
at factory-programmed time intervals of at least 24 hours. The Battery Low (BL) pin will be
asserted if the battery voltage is found to be less than approximately 2.5V. The BL pin will
remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the next power-up sequence or the next scheduled 24-hour
interval.
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted).
Min
Max
Unit
tRLRH
(2)
2.
Pulse width less than 50ns will result in no RESET (for noise immunity).
RSTIN low to RSTIN high
200
ns
tR1HRH
(3)
3.
CL = 5pF (see Figure 10 on page 16).
RSTIN high to RST high
40
200
ms
AI04768
RST
(1)
RSTIN
tRLRH
tR1HRH



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