IMX93CEC datasheet(36/123 Pages) NXP

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SWD_CLK (input)

SWD_DIO (input)

SWD_DIO (output)

Figure 13. SWD timing

Table 33 lists SWD timing parameters.

Table 33. SWD timing parameters[1],[2]

Symbol

Description

Min

Max

Unit

SWD_CLK frequency

—

MHz

SWD_CLK cycle time

—

SWD_CLK pulse width

—

Input data setup time

—

Input data hold time

—

Output data valid time

—

Output high impedance time

—

Output data invalid time

—

[1] Input timing assumes an input signal slew rate of 3 ns (20%/80%).

[2] Timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 Ω, unterminated, 5-inch microstrip trace on standard

FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in the transmission line can be equal to the selected RDSON of the

I/O pad output.

4.8.5 DDR SDRAM–specific parameters (LPDDR4/LPDDR4X)

The i.MX 93 Family of processors have been designed and tested to work with JEDEC JESD209—compliant LPDDR4/

LPDDR4X memory.

• JEDEC LPDDR4 Specification JESD209-4B, February 2017

• JEDEC LPDDR4X Specification JESD209-4-1, January 2017

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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