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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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IMX93CEC Datenblatt(PDF) 39 Page - NXP Semiconductors |
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IMX93CEC Datenblatt(HTML) 39 Page - NXP Semiconductors |
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39 / 123 page  Table 38. MIPI high-speed receiver AC specifications Symbol Parameter Min Typ Max Unit ΔVCMRX(HF)[1] Common mode interference beyond 450 MHz — — 50 mV ΔVCMRX(LF) Common mode interference between 50 and 450 MHz -25 — 25 mV CCM Common mode termination — — 60 pF [1] ΔVCMRX(HF) is the peak amplitude of a sine wave superimposed on the receiver inputs. 4.9.1.3 MIPI LP-TX specifications Table 39. MIPI low-power transmitter DC specifications Symbol Parameter Min Typ Max Unit VOH[1] Thevenin Output High Level 1.1 1.2 1.3 V VOL Thevenin Output Low Level –50 — 50 mV ZOLP[2] Output Impedance of Low Power Transmitter 110 — — Ω [1] This specification can only be met when limiting the core supply variation from 1.1 V till 1.3 V. [2] Although there is no specified maximum for ZOLP, the LP transmitter output impedance ensures the TRLP/TFLP specification is met. Table 40. MIPI low-power transmitter AC specifications Symbol Parameter Min Typ Max Unit TRLP/TFLP[1] 15% to 85% Rise Time and Fall Time — — 25 ns TREOT1,[2],[3] 30% to 85% Rise Time and Fall Time — — 35 ns TLP-PULSE- TX [4] Pulse width of the LP exclusive-OR clock: First LP exclusive-OR clock pulse after Stop state or last pulse before Stop state 40 — — ns Pulse width of the LP exclusive-OR clock: All other pulses 20 — — ns TLP-PER-TX Period of the LP exclusive-OR clock 90 — — ns δV/ δtSR1,[5],[6],[7] Slew Rate @ CLOAD= 0 pF 25 — 500 mV/ns Slew Rate @ CLOAD= 5 pF 25 — 300 mV/ns Slew Rate @ CLOAD= 20 pF 25 — 250 mV/ns Slew Rate @ CLOAD= 70 pF 25 — 150 mV/ns CLOAD Load Capacitance 0 — 70 pF [1] CLOAD includes the low equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be < 10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay. [2] The rise-time of TREOT starts from the HS common-level at the moment of the differential amplitude drops below 70 mV, due to stopping the differential drive. [3] With an additional load capacitance CCM between 0 to 60 pF on the termination center tap at RX side of the lane. [4] This parameter value can be lower then TLPX due to differences in rise vs. fall signal slopes and trip levels and mismatches between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11) is glitch behavior as described in Low-Power Receiver section. [5] When the output voltage is between 15% and below 85% of the fully settled LP signal levels. [6] Measured as average across any 50 mV segment of the output signal transition. NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 39 / 123 |
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