IMX93CEC datasheet(43/123 Pages) NXP

43 / 123 page

S10

SAI_MCLK (output)

SAI_BCLK (output)

SAI_FS (output)

SAI_FS (input)

SAI_TXD

SAI_RXD

Figure 15. SAI timing—Controller mode

Table 47. Target mode SAI timing (25 MHz)[1][2]

Num

Characteristic

Min

Max

Unit

S11

SAI_BCLK cycle time (input)

—

S12

SAI_BCLK pulse width high/low (input)

40%

60%

BCLK period

S13

SAI_FS input setup before SAI_BCLK

—

S14

SAI_FS input hold after SAI_BCLK

—

S15

SAI_BCLK to SAI_TXD/SAI_FS output valid

—

S16

SAI_BCLK to SAI_TXD/SAI_FS output invalid

—

S17

SAI_RXD setup before SAI_BCLK

—

S18

SAI_RXD hold after SAI_BCLK

—

S19

SAI_FS input assertion to SAI_TXD output valid[3]

—

[1] Input timing assumes an input signal slew rate of 3 ns (20%/80%).

[2] Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm. Unterminated, 5-inch microstrip trace

on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in the transmission line should be equal to the selected

RDSON of the I/O pad output driver.

[3] Applies to first bit in each frame and only if the TCR4[FSE] bit is clear.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

Document feedback

43 / 123

IMX93CEC Datenblatt(PDF) 43 Page - NXP Semiconductors

IMX93CEC Datenblatt(HTML) 43 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL