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EM78F651NAMS/NAMJ Datenblatt(PDF) 18 Page - ELAN Microelectronics Corp |
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EM78F651NAMS/NAMJ Datenblatt(HTML) 18 Page - ELAN Microelectronics Corp |
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18 / 58 page ![]() EM78F651N 8-Bit Microcontroller 14 • Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) 6.2.3 IOC5 ~ IOC7 (I/O Port Control Register) A value of "1" sets the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. Only Bits 4, 5 of R5 are available (EM78F651NA) Only Bits 0, 3, 4, 5 of IOC5 can be defined (EM78F651NB) Only the lower 6 bits of IOC5 can be defined (EM78F651NC) Only Bit 0 of IOC7 is available, when P7.0 is set as output, a pull-high resistor must be tied to Vdd, since this is an internal open-drain circuit. IOC5 and IOC7 registers are both readable and writable. 6.2.4 IOCA (WDT Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTE EIS - - PSWE PSW2 PSW1 PSW0 Bit 7 (WDTE) Control bit used to enable the Watchdog timer 0 : Disable WDT 1 : Enable WDT WDTE is both readable and writable. Bit 6 (EIS): Control bit used to define the function of P60 (/INT) pin 0 : P60, bidirectional I/O pin 1 : /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC6) must be set to "1". When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig 6-5 (a). EIS is both readable and writable. Bits 5~4: Not used, set to “0” at all time Bit 3 (PSWE): Prescaler enable bit for WDT 0 : prescaler disable bit, WDT rate is 1:1 1 : prescaler enable bit, WDT rate is set as Bit 0~Bit 2 Bit 2 (PSW2) ~ Bit 0 (PSW0): WDT prescaler bits PSW2 PSW1 PSW0 WDT Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 |
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