EM78F651NAMSSLASHNAMJ datasheet(49/58 Pages) EMC

49 / 58 page

EM78F651N

8-Bit Microcontroller

Product Specification (V1.1) 10.20.2006

• 45

(This specification is subject to change without further notice)

EM78F651N

/RESET

Vdd

40K

Fig. 6-17 Circuit 2 for the Residue Voltage Protection

6.14 Instruction Set

Each instruction in the instruction set is a 13-bit word divided into an OP code and

one or more operands. Normally, all instructions are executed within one single

instruction cycle (one instruction consists of two oscillator periods), unless the

program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by

instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6",

"CLR R2", etc.). In this case, the execution takes two instruction cycles.

If for some reasons, the specification of the instruction cycle is not suitable for certain

applications, try modifying the instruction as follows:

(A) Change one instruction cycle to consist of four oscillator periods.

(B) "JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip ("JBS", "JBC", "JZ",

"JZA", "DJZ", "DJZA") commands which were tested to be true, are executed

within two instruction cycles. The instructions that are written to the program

counter also take two instruction cycles.

Case (A) is selected by the Code Option bit, called CLK. One instruction cycle

consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is

high.

Note that once the four oscillator periods within one instruction cycle is selected

as in Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead

of Fosc / 2 as indicated in Fig 6-3.

In addition, the instruction set has the following features:

(1) Every bit of any register can be set, cleared, or tested directly.

(2) The I/O register can be regarded as general register. That is, the same instruction

can operate on the I/O register.

EM78F651NAMS/NAMJ Datenblatt(PDF) 49 Page - ELAN Microelectronics Corp