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HD6432351 Datenblatt(PDF) 217 Page - Renesas Technology Corp

Teilenummer HD6432351
Bauteilbeschribung  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 Datenblatt(HTML) 217 Page - Renesas Technology Corp

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Section 6 Bus Controller
Rev. 3.00 Sep 15, 2006 page 183 of 988
REJ09B0330-0300
(3) Relationship between Chip Select (
CS
CS
CS
CS) Signal and Read (RD
RD
RD
RD) Signal
Depending on the system’s load conditions, the
RD signal may lag behind the CS signal. An
example is shown in figure 6.33.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A
RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the
RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
T1
Address bus
φ
RD
Bus cycle A
T2
T3
T1
T2
Bus cycle B
Possibility of overlap between
CS (area B) and RD
T1
Address bus
φ
Bus cycle A
T2
T3
TI
T1
Bus cycle B
T2
CS (area A)
CS (area B)
RD
CS (area A)
CS (area B)
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 6.33 Relationship between Chip Select (
CS
CS
CS
CS) and Read (RD
RD
RD
RD)



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