HD6432351 datasheet(23/1025 Pages) RENESAS

23 / 1025 page

Rev. 3.00 Sep 15, 2006 page xxiii of xxxiv

6.8

Idle Cycle .......................................................................................................................... 181

6.8.1

Operation ............................................................................................................. 181

6.8.2

Pin States in Idle Cycle ........................................................................................ 186

6.9

Write Data Buffer Function............................................................................................... 187

6.10 Bus Release....................................................................................................................... 188

6.10.1 Overview.............................................................................................................. 188

6.10.2 Operation ............................................................................................................. 188

6.10.3 Pin States in External Bus Released State............................................................ 189

6.10.4 Transition Timing ................................................................................................ 190

6.10.5 Usage Note........................................................................................................... 190

6.11 Bus Arbitration.................................................................................................................. 191

6.11.1 Overview.............................................................................................................. 191

6.11.2 Operation ............................................................................................................. 191

6.11.3 Bus Transfer Timing ............................................................................................ 192

6.11.4 External Bus Release Usage Note........................................................................ 193

6.12 Resets and the Bus Controller ........................................................................................... 193

Section 7 DMA Controller (DMAC) ............................................................................. 195

7.1

Overview........................................................................................................................... 195

7.1.1

Features................................................................................................................ 195

7.1.2

Block Diagram ..................................................................................................... 196

7.1.3

Overview of Functions ......................................................................................... 197

7.1.4

Pin Configuration................................................................................................. 199

7.1.5

7.2

7.2.1

Memory Address Registers (MAR)...................................................................... 202

7.2.2

I/O Address Register (IOAR)............................................................................... 203

7.2.3

Execute Transfer Count Register (ETCR)............................................................ 203

7.2.4

DMA Control Register (DMACR)....................................................................... 205

7.2.5

DMA Band Control Register (DMABCR)........................................................... 209

7.3

7.3.1

Memory Address Register (MAR) ....................................................................... 215

7.3.2

I/O Address Register (IOAR)............................................................................... 215

7.3.3

Execute Transfer Count Register (ETCR)............................................................ 216

7.3.4

DMA Control Register (DMACR)....................................................................... 218

7.3.5

DMA Band Control Register (DMABCR)........................................................... 222

7.4

Register Descriptions (3)................................................................................................... 228

7.4.1

DMA Write Enable Register (DMAWER) .......................................................... 228

7.4.2

DMA Terminal Control Register (DMATCR)..................................................... 231

7.4.3

Module Stop Control Register (MSTPCR) .......................................................... 232

7.5

Operation........................................................................................................................... 233

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