H8SXSLASH1663 datasheet(350/1158 Pages) RENESAS

Teilenummer	H8SX/1663

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 298 of 1102

REJ09B0294-0100

(6) Relationship between Chip Select (

CS) Signal and Read (RD) Signal

Depending on the system's load conditions, the

RD signal may lag behind the CS signal. An

example is shown in figure 6.95. In this case, with the setting for no idle cycle insertion (a), there

may be a period of overlap between the

RD signal in bus cycle A and the CS signal in bus cycle B.

Setting idle cycle insertion, as in (b), however, will prevent any overlap between the

RD and CS

signals. In the initial state after reset release, idle cycle indicated in (b) is set.

Bus cycle A

Bus cycle B

Address bus

CS (area A)

CS (area B)

Bus cycle A

Bus cycle B

Overlap time may occur between the

CS (area B) and RD

(a) No idle cycle inserted

(IDLS1 = 0)

(b) Idle cycle inserted

(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)

Figure 6.95 Relationship between Chip Select (

CS) and Read (RD)

H8SX/1663 Datenblatt(PDF) 350 Page - Renesas Technology Corp