H8SXSLASH1663 datasheet(354/1158 Pages) RENESAS

354 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 302 of 1102

REJ09B0294-0100

Table 6.30

Idle Cycles in Mixed Accesses to Normal Space and DRAM/SDRAM Space

IDLS

IDLSEL

IDLCA

IDLCB

Access

Next Access

7 to 0

Idle Cycle



Disabled



1 cycle inserted

Normal/DRAM/

SDRAM space

read

Normal/DRAM/

SDRAM space

read

2 cycles inserted

3 cycles inserted

4 cycles inserted



0 cycle inserted

2 cycles inserted

3 cycles inserted

4 cycles inserted



Disabled



1 cycle inserted

Normal/DRAM/

SDRAM space

read

Normal/DRAM/

SDRAM space

read

2 cycles inserted

3 cycles inserted

4 cycles inserted

0 cycle inserted

2 cycles inserted

3 cycles inserted

4 cycles inserted



Disabled



1 cycle inserted

Normal/DRAM/

SDRAM space

write

Normal/DRAM/

SDRAM space

read

2 cycles inserted

3 cycles inserted

4 cycles inserted



Disabled

Single address

write

Normal/DRAM/

SDRAM space

write



1 cycle inserted

2 cycles inserted

3 cycles inserted

4 cycles inserted

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