H8SXSLASH1663 datasheet(360/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 308 of 1102

REJ09B0294-0100

6.14

Internal Bus

6.14.1

Access to Internal Address Space

The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and

differs according the space.

Table 6.33 shows the number of access cycles for each on-chip memory space.

Table 6.33

Number of Access Cycles for On-Chip Memory Spaces

Access Space

Access

Number of Access Cycles

Read

One I

φ cycle

On-chip ROM space

Write

Three I

φ cycles

Read

One I

φ cycle

On-chip RAM space

Write

One I

φ cycle

In access to the registers for on-chip peripheral modules, the number of access cycles differs

according to the register to be accessed. When the dividing ratio of the operating clock of a bus

master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0

to n-1 are inserted for register access in the same way as for external bus clock division.

Table 6.34 lists the number of access cycles for registers of on-chip peripheral modules.

Table 6.34

Number of Access Cycles for Registers of On-Chip Peripheral Modules

Number of Cycles

Module to be Accessed

Read

Write

Write Data Buffer Function

DMAC registers

Two I

Disabled

MCU operating mode, clock pulse generator,

power-down control registers, interrupt controller,

bus controller, and DTC registers

Two I

Three I

φ Disabled

I/O port registers of PFCR and WDT

Two P

Three P

φ Disabled

I/O port registers other than PFCR and PORTM,

TPU, PPG, TMR, SCI, SCI0 to SCI2, SCI4, A/D,

and D/A registers

Two P

Enabled

I/O port registers of PORTM,

USB, SCI5, and SCI6

Three P

Enabled

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