H8SXSLASH1663 datasheet(358/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 306 of 1102

REJ09B0294-0100

6.13.3

Transition Timing

Figures 6.99 and 6.100 show the timing of transition to the bus released state.

Address bus

CSn

LHWR, LLWR

Hi-Z

[1]

[2]

[3]

[4]

[7]

[5]

[6]

[8]

Hi-Z

BREQ

BACK

BREQO

External space

access cycle

CPU cycle

External bus released state

Data bus

[1] A low level of the

BREQ signal is sampled at the rising edge of the Bφ signal.

[2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or

more after the low level of the

BREQ signal is sampled.

[3] The

BACK signal is driven low, releasing bus to the external bus master.

[4] The

BREQ signal state sampling is continued in the external bus released state.

[5] A high level of the

BREQ signal is sampled.

[6] The external bus released cycles are ended one cycle after the

BREQ signal is driven high.

[7] When the external space is accessed by an internal bus master during external bus released while the BREQOE

bit is set to 1, the

BREQO signal goes low.

[8] Normally the

BREQO signal goes high at the rising edge of the BACK signal.

Figure 6.99 Bus Released State Transition Timing (SRAM Interface is Not Used)

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