H8SXSLASH1663 datasheet(356/1158 Pages) RENESAS

356 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 304 of 1102

REJ09B0294-0100

6.13

Bus Release

This LSI can release the external bus in response to a bus request from an external device. In the

external bus released state, the internal bus master continue operation as long as there is no

external access.

In addition, in the external bus released state, the

BREQO signal can be driven low to output a bus

request externally.

6.13.1

Operation

In external extended mode, when the BRLE bit in BCR1 is set to 1, and the ICR bit for the

corresponding pin is set to 1, the bus can be released to the external. Driving the

BREQ pin low

issues an external bus request to this LSI. When the

BREQ pin is sampled, at the prescribed

timing, the

BACK pin is driven low, and the address bus, data bus, and bus control signals are

placed in the high-impedance state, establishing the external bus released state. For ICR, see

section 9, I/O Ports.

In the external bus released state, the CPU, DTC, and DMAC can access the internal space using

the internal bus. When any one of the CPU, DTC, and DMAC attempts to accesses the external

address space, it temporarily defers initiation of the bus cycle, and waits for the bus request from

the external bus master to be canceled.

In the external bus released state, certain operations are suspended as follows until the bus request

from the external bus master is canceled:

• When a refresh is requested, refresh control is suspended.

• When the SLEEP instruction is executed to enter software standby mode or all-module clock-

stop mode, control for software standby mode or all-module clock-stop mode is suspended.

• When SCKCR is written to set the clock frequencies, changing of clock frequencies is

suspended. For SCKCR, see section 22, Clock Pulse Generator.

If the BREQOE bit in BCR1is set to 1, the

BREQO pin can be driven low to request cancellation

of the bus request when any of the following requests are issued.

• When any one of the CPU, DTC, and DMAC attempts to access the external address space

• When a refresh is requested

• When a SLEEP instruction is executed to place the chip in software standby mode or all-

module-clock-stop mode

• When SCKCR is written to set the clock frequencies

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