H8SXSLASH1663 datasheet(368/1158 Pages) RENESAS

368 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 316 of 1102

REJ09B0294-0100

(9) Switching Between Refresh Timer and Interval Timer

When changing the RFSHE bit in REFCR from 1 to 0, a refresh cycle may be inserted until the bit

change is reflected. After this, when using RTCNT as an interval timer, the compare match flag

(CMF) may be set to 1. Therefore, confirm the state before setting the CMIE bit to 1.

(10) RAS Down Mode and Software Standby Mode for DRAM Interface

When making a transition to software standby mode with the OPE bit in SBYCR set to 0 without

using the self-refresh mode, the transition should be made in RAS up mode (RCDM

= 0). When

RAS down mode (RCDM

= 1) is used, execute the SLEEP instruction after setting the RCDM bit

to 0. RAS down mode should be set again after recovery from software standby mode. For

SBYCR, see section 23, Power-Down Modes.

(11) RAS Down Mode and Clock Frequencies Setting for DRAM/SDRAM

Write access to SCKCR for setting the clock frequencies should be performed in RAS up mode

(RCDM

= 0). When RAS down mode (RCDM = 1) is used, set the RCDM bit to 0 before writing

to SCKCR. RAS down mode should be set again after clock frequencies are set. For SCKCR, see

section 22, Clock Pulse Generator.

(12) Cluster Transfer to SDRAM Space

Cluster transfer mode is available for the SDRAM with CAS latency of 2. When the SDRAM is

used in cluster transfer mode, the SDRAM with CAS latency of 2 should be used. In cluster

transfer mode, the write-precharge output delay function by the TRWL bit is not available. The

TRWL bit must be cleared to 0.

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