H8SXSLASH1663 datasheet(394/1158 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 342 of 1102

REJ09B0294-0100

7.3.8

DMA Module Request Select Register (DMRSR)

DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source.

The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no

interrupt source. For the vector numbers of the interrupt sources, refer to table 7.5.

R/W

Bit

Bit Name

Initial Value

R/W

7.4

Transfer Modes

Table 7.4 shows the DMAC transfer modes. The transfer modes can be specified to the individual

channels.

Table 7.4

Transfer Modes

Address Register

Address

Mode

Transfer mode

Activation Source

Common Function

Source

Destina-

tion

Dual

address

• Normal transfer

• Repeat transfer

• Block transfer

Repeat or block size

= 1 to 65,536 bytes,

1 to 65,536 words, or

1 to 65,536

longwords

• Auto request

(activated by

CPU)

• On-chip module

interrupt

• External request

• Total transfer

size: 1 to 4

Gbytes or not

specified

• Offset addition

• Extended repeat

area function

DSAR

DDAR

Single

address

• Instead of specifying the source or destination address

registers, data is directly transferred from/to the external

device using the

DACK pin

• The same settings as above are available other than address

• One transfer can be performed in one bus cycle (the types of

transfer modes are the same as those of dual address modes)

DSAR/

DACK

DACK/

DDAR

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