H8SXSLASH1663 datasheet(396/1158 Pages) RENESAS

396 / 1158 page

Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 344 of 1102

REJ09B0294-0100

Address bus

TEND

DMA read

cycle

DMA write

cycle

DSAR

DDAR

Figure 7.2 Example of Signal Timing in Dual Address Mode

Transfer

Address TA

Address BA

Address update setting is as follows:

Source address increment

Fixed destination address

Address TB

Figure 7.3 Operations in Dual Address Mode

(2) Single Address Mode

In single address mode, data between an external device and an external memory is directly

transferred using the

DACK pin instead of DSAR or DDAR. A transfer at a time is performed in

one bus cycle. In this mode, the data bus width must be the same as the data access size. For

details on the data bus width, see section 6, Bus Controller (BSC).

The DMAC accesses an external device as the transfer source or destination by outputting the

strobe signal (

DACK) to the external device with DACK and accesses the other transfer target by

outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 7.4

shows an example of a transfer between an external memory and an external device with the

DACK pin. In this example, the external device outputs data on the data bus and the data is written

to the external memory in the same bus cycle.

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