H8SXSLASH1663 datasheet(401/1158 Pages) RENESAS

401 / 1158 page

Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 349 of 1102

REJ09B0294-0100

Transfer

Address TA

Address TB

Address BB

Address BA

Operation when the repeat area is specified

to the source side

Repeat size =

BKSZH

data access size

Total transfer

size (DTCR)

Figure 7.9 Operations in Repeat Transfer Mode

(3) Block Transfer Mode

In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4

Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR

up to 65536

× data access size.

While one block of data is being transferred, transfer requests from other channels are suspended.

When the transfer is completed, the bus is released to the other bus master.

The block area can be specified for the source or destination address side by bits ARS1 and ARS0

in DACR. The address specified as the block area returns to the transfer start address when the

block size of data is completed. When the block area is specified as neither source nor destination

address side, the operation continues without returning the address to the transfer start address. A

repeat size end interrupt can be requested.

The

TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle.

When the external request is selected as an activation source, the low level detection of the

DREQ

signal (DREQS = 0) should be selected.

When an interrupt request by an extended repeat area overflow is used in block transfer mode,

settings should be selected carefully. For details, see section 7.5.5, Extended Repeat Area

Function.

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