H8SXSLASH1663 datasheet(448/1158 Pages) RENESAS

448 / 1158 page

Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 396 of 1102

REJ09B0294-0100

Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to

the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus

connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC

transfer information.

Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR

must be set to 1.

Bus interface

Bus controller

DTCCR

Interrupt controller

ACK

REQ

DTCVBR

DTC

CPU interrupt request

Interrupt source clear

request

control

Activation

control

Interrupt

control

On-chip

ROM

On-chip

RAM

MRA

MRB

SAR

DAR

CRA

CRB

On-chip

peripheral

module

External

memory

External device

(memory mapped)

DTC activation request

vector number

MRA, MRB:

SAR:

DAR:

CRA, CRB:

DTCERA to DTCERE,

DTCERG, and DTCERH:

DTCCR:

DTCVBR:

DTC mode registers A, B

DTC source address register

DTC destination address register

DTC transfer count registers A, B

DTC enable registers A to E, G, and sH

DTC control register

DTC vector base register

[Legend]

DTCERA to DTCERE,

DTCERG, and DTCERH

Figure 8.1 Block Diagram of DTC

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