H8SXSLASH1663 datasheet(452/1158 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 400 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

DM1

DM0

Undefined



Destination Address Mode 1 and 0

Specify a DAR operation after a data transfer.

0X: DAR is fixed

(DAR writeback is skipped)

10: DAR is incremented after a transfer

(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and

Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)

11: SAR is decremented after a transfer

(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and

Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)

1, 0



Undefined



Reserved

The write value should always be 0.

[Legend]

X: Don't care

8.2.3

DTC Source Address Register (SAR)

SAR is a 32-bit register that designates the source address of data to be transferred by the DTC.

In full address mode, 32 bits of SAR are valid. In short address mode, the lower 24 bits of SAR is

valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of

bit 23.

If a word or longword access is performed while an odd address is specified in SAR or if a

longword access is performed while address 4n + 2 is specified in SAR, the bus cycle is divided

into multiple cycles to transfer data. For details, see section 8.5.1, Bus Cycle Division.

SAR cannot be accessed directly from the CPU.

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