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H8SX/1663 Datenblatt(PDF) 450 Page - Renesas Technology Corp

Teilenummer H8SX/1663
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663 Datenblatt(HTML) 450 Page - Renesas Technology Corp

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Section 8 Data Transfer Controller (DTC)
Rev.1.00 Jun. 07, 2006 Page 398 of 1102
REJ09B0294-0100
8.2.1
DTC Mode Register A (MRA)
MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU.
Bit
Bit Name
Initial Value
R/W
7
MD1
Undefined
6
MD0
Undefined
5
Sz1
Undefined
4
Sz0
Undefined
3
SM1
Undefined
2
SM0
Undefined
1
Undefined
0
Undefined
Bit
Bit Name
Initial
Value
R/W
Description
7
6
MD1
MD0
Undefined
Undefined
DTC Mode 1 and 0
Specify DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
5
4
Sz1
Sz0
Undefined
Undefined
DTC Data Transfer Size 1 and 0
Specify the size of data to be transferred.
00: Byte-size transfer
01: Word-size transfer
10: Longword-size transfer
11: Setting prohibited
3
2
SM1
SM0
Undefined
Undefined
Source Address Mode 1 and 0
Specify an SAR operation after a data transfer.
0x: SAR is fixed
(SAR writeback is skipped)
10: SAR is incremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
11: SAR is decremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
1, 0
Undefined
Reserved
The write value should always be 0.
[Legend]
X: Don't care



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