H8SXSLASH1663 datasheet(476/1158 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 424 of 1102

REJ09B0294-0100

8.7

Examples of Use of the DTC

8.7.1

Normal Transfer Mode

An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.

1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =

1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The

DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0,

DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where

the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value.

2. Set the start address of the transfer information for an RXI interrupt at the DTC vector address.

3. Set the corresponding bit in DTCER to 1.

4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the receive

end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation

will disable subsequent reception, the CPU should be enabled to accept receive error

interrupts.

5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an

RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR

to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is

automatically cleared to 0.

6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the

DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination

processing should be performed in the interrupt handling routine.

8.7.2

Chain Transfer

An example of DTC chain transfer is shown in which pulse output is performed using the PPG.

Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle

updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain

transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing

of the activation source and interrupt generation at the end of the specified number of transfers are

restricted to the second half of the chain transfer (transfer when CHNE = 0).

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