H8SXSLASH1663 datasheet(477/1158 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 425 of 1102

REJ09B0294-0100

1. Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing

(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,

MD0 = 1), and word size (Sz1 = 0, Sz0 = 1). Set the source side as a repeat area (DTS = 1). Set

MRB to chain transfer mode (CHNE = 1, CHNS = 0, DISEL = 0). Set the data table start

address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL.

CRB can be set to any value.

2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing

(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0

= 0), and word size (Sz1 = 0, Sz0 = 1). Set the data table start address in SAR, the TGRA

address in DAR, and the data table size in CRA. CRB can be set to any value.

3. Locate the TPU transfer information consecutively after the NDR transfer information.

4. Set the start address of the NDR transfer information to the DTC vector address.

5. Set the bit corresponding to the TGIA interrupt in DTCER to 1.

6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA

interrupt with TIER.

7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and

NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to

be used as the output trigger.

8. Set the CST bit in TSTR to 1, and start the TCNT count operation.

9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the

set value of the next output trigger period is transferred to TGRA. The activation source TGFA

flag is cleared.

10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the

TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the

CPU. Termination processing should be performed in the interrupt handling routine.

8.7.3

Chain Transfer when Counter = 0

By executing a second data transfer and performing re-setting of the first data transfer only when

the counter value is 0, it is possible to perform 256 or more repeat transfers.

An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed

to have been set to start at lower address H'0000. Figure 8.16 shows the chain transfer when the

counter value is 0.

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