H8SXSLASH1663 datasheet(479/1158 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 427 of 1102

REJ09B0294-0100

8.8

Interrupt Sources

An interrupt request is issued to the CPU when the DTC finishes the specified number of data

transfers or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,

the interrupt set as the activation source is generated. These interrupts to the CPU are subject to

CPU mask level and priority level control in the interrupt controller.

8.9

Usage Notes

8.9.1

Module Stop State Setting

Operation of the DTC can be disabled or enabled using the module stop control register. The

initial setting is for operation of the DTC to be enabled. Register access is disabled by setting the

module stop state. The module stop state cannot be set while the DTC is activated. For details,

refer to section 23, Power-Down Modes.

8.9.2

On-Chip RAM

Transfer information can be located in on-chip RAM. In this case, the RAME bit in SYSCR must

not be cleared to 0.

8.9.3

DMAC Transfer End Interrupt

When the DTC is activated by a DMAC transfer end interrupt, the DTE bit of DMDR is not

controlled by the DTC but its value is modified with the write data regardless of the transfer

counter value and DISEL bit setting. Accordingly, even if the DTC transfer counter value

becomes 0, no interrupt request may be sent to the CPU in some cases.

8.9.4

DTCE Bit Setting

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts

are disabled, multiple activation sources can be set at one time (only at the initial setting) by

writing data after executing a dummy read on the relevant register.

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