H8SXSLASH1663 datasheet(481/1158 Pages) RENESAS

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Section 9 I/O Ports

Rev.1.00 Jun. 07, 2006 Page 429 of 1102

REJ09B0294-0100

Section 9 I/O Ports

Table 9.1 summarizes the port functions. The pins of each port also have other functions such as

input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port

includes a data direction register (DDR) that controls input/output, a data register (DR) that stores

output data, a port register (PORT) used to read the pin states, and an input buffer control register

(ICR) that controls input buffer on/off. Port 5 does not have a DR or a DDR register.

Ports D to F, H, and I have internal input pull-up MOSs and a pull-up MOS control register (PCR)

that controls the on/off state of the input pull-up MOSs.

Ports 2 and F include an open-drain control register (ODR) that controls on/off of the output

buffer PMOSs.

All of the I/O ports can drive a single TTL load and capacitive loads up to 30 pF.

All of the I/O ports can drive Darlington transistors when functioning as output ports.

Port 2 and 3 are Schmitt-trigger input. Schmitt-trigger inputs for other ports are enabled when

used as the

IRQ, TPU, TMR, or IIC2 inputs.

Table 9.1

Port Functions

Function

Port

Description

Bit

I/O

Input

Output

Schmitt-

Trigger

Input*

Input

Pull-up

MOS

Function

Open-

Drain

Output

Function

Port 1

P17/SCL0

IRQ7-A/

TCLKD-B



IRQ7-A,

TCLKD-B,

SCL0



P16/SDA0

IRQ6-A/

TCLKC-B

DACK1-A

IRQ6-A,

TCLKC-B,

SDA0

General I/O port

also functioning

as interrupt inputs,

SCI I/Os, DMAC

I/Os, A/D

converter inputs,

TPU inputs, and

IIC2 I/Os

P15/SCL1

IRQ5-A/

TCLKB-B/

RxD5/

IrRXD

TEND1-A

IRQ5-A,

TCLKB-B,

SCL1

P14/SDA1

DREQ1-A/

IRQ4-A/

TCLKA-B

TxD5/

IrTxD

IRQ4-A,

TCLKA-B,

SDA1

P13

ADTRG0/

IRQ3-A



IRQ3-A

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